The present invention relates to a semiconductor device having a three-layer structure of metal-insulator-semiconductor, and a method for manufacturing the same, and more particularly to a field effect transistor using a metal oxide film having a high dielectric constant as a gate insulating film material, and a method for manufacturing the same.
A type of field effect transistor (hereinafter referred to as “FET”) used in the prior art is a MOSFET having a three-layer structure of metal-insulator-semiconductor. As MOSFETs are miniaturized at a significant rate, the thickness of a conventional gate oxide film has been reduced at an accelerated rate. The thickness of a gate oxide film is now as small as about 2 nm. However, when the physical thickness of a gate oxide film is reduced below about 2 nm, the transmittance of electrons through the gate oxide film increases dramatically, resulting in an excessive tunnel leak current flowing between the gate electrode and the substrate, which makes it difficult to even realize a transistor operation of the MOSFET. Moreover, when the physical thickness of a gate oxide film is reduced below about 2 nm, it is no longer possible to maintain the uniformity in the thickness of the gate oxide film. These problems mean that one can no longer expect the main purpose of a MOSFET, i.e., to increase the on state current. In order to overcome such a physical limit, attempts have been made quite recently to use an insulative film having a higher dielectric constant than a silicon oxide film (a high-k film) as a gate insulating film. These attempts aim to realize a physical thickness that is larger than the limit value (about 2 nm) and a large capacitance of gate insulating film, thereby making it possible to obtain a large on state current while suppressing the leak current as much as possible. Note that a high-k film is typically an insulative metal oxide film.
A semiconductor device of a first conventional example, specifically a MOSFET using a high-k gate insulating film, will now be described with reference to the drawings.
FIG. 4A to FIG. 4D are cross-sectional views of a gate section, illustrating steps in a method for manufacturing the semiconductor device of the first conventional example. Note that steps such as the well formation, the isolation formation, the ion implantation for threshold control, and also the contact formation and the subsequent steps, will not be described below.
First, a silicon substrate 50 is prepared, as illustrated in FIG. 4A, and then an HfO2 film 51 is formed on the silicon substrate 50 by using a chemical vapor deposition method (hereinafter referred to as “CVD method”), as illustrated in FIG. 4B. Specifically, a CVD process is performed at 500° C. in an oxygen gas atmosphere using Hf(OC(CH3)3)4 (hereinafter referred to as “Hf-t-butoxide”) as a material so as to deposit the HfO2 film 51 having a thickness of 6 nm. In this process, a hafnium silicate (HfSixOy (where x+y=1, x>0, y>0)) layer 52 is necessarily formed between the silicon substrate 50 and the HfO2 film 51, i.e., at an interface of the silicon substrate 50 with the HfO2 film 51, by an interface reaction occurring due to the CVD process. The two-layer structure of the upper HfO2 film 51 and the lower HfSixOy layer 52 provides a high-k gate insulating film. Typically, the HfO2 film 51 is a polycrystalline layer, and the HfSixOy layer 52 is an amorphous layer. Note that in a case where a physical vapor deposition method (hereinafter referred to as “PVD method”) is used instead of a CVD method, the degree of crystallization of the HfO2 film immediately after deposition is slightly lower than that when a CVD method is used.
Then, the HfO2 film 51 is subjected to a heat treatment for 30 seconds at 800° C. in a nitrogen gas atmosphere so as to stabilize the stoichiometric composition ratio of the HfO2 film 51. Then, a conductive film made of a conductive material such as polysilicon is deposited on the HfO2 film 51, and then the conductive film is patterned by dry-etching so as to form a gate electrode 53, as illustrated in FIG. 4C. In this process, a portion of each of the HfO2 film 51 and the HfSixOy layer 52 that is located outside the gate electrode 53 is removed.
Then, a silicon oxide film is formed on the surface of the silicon substrate 50, including the surface of the gate electrode 53, and then the silicon oxide film is etched back so that the silicon oxide film is left unremoved only on the side surface of the gate electrode 53, thereby forming a sidewall 54, as illustrated in FIG. 4D. Then, an ion implantation process is performed on the silicon substrate 50 so that a source region 55 and a drain region 56, in which an impurity is diffused at a high concentration, are formed in upper portions of the silicon substrate 50 that are on opposite sides of the gate electrode 53. In this process, ions are also implanted into the polysilicon film forming an upper portion of the gate electrode 53. Then, a heat treatment is performed on the silicon substrate 50 at 900° C. in a nitrogen gas atmosphere so as to activate the impurity contained in each of the gate electrode 53, the source region 55 and the drain region 56. Note that the sidewall 54 prevents ions from being implanted into a side portion of each of the HfO2 film 51 and the HfSixOy layer 52, which remain under the gate electrode 53, i.e., into a side portion of the gate insulating film.
A MOSFET produced as described above is turned ON/OFF by the presence/absence of a channel 57 in a portion of the silicon substrate 50 immediately under the gate electrode 53, which is, or is not, formed depending on the level of the voltage applied to the gate electrode 53 (hereinafter referred to as “gate voltage”). The level “Idmax” of the on state current, which flows through the channel 57 when the transistor is ON is expressed as follows:Idmax=(½)·μ·(W/L)·Cox·(Vg−Vth)2
where μ is the carrier mobility through the inversion layer to be the channel, W is the gate width of the transistor, L is the gate length of the transistor, Cox is the capacitance of the gate insulating film (hereinafter referred to as “gate capacitance”), Vg is the gate voltage, and Vth is the threshold voltage.
It can be seen from the expression above that it is important to increase μ, W, Cox or (Vg−Vth), or to decrease L, in order to obtain a larger on state current. Herein, in order to increase Cox, it is necessary to increase the relative dielectric constant εr of the gate insulating film, or to decrease the physical thickness Tox of the gate insulating film. Thus, among the factors mentioned above, those that are related to the gate insulating film are an increase in μ, an increase in the relative dielectric constant εr, and a decrease in the physical thickness Tox of the gate insulating film. In view of this, attempts have been made in the prior art in order to improve the on state current, such as increasing μ by flattening the interface between the gate oxide film and the silicon substrate, or realizing a super thin gate oxide film by decreasing the physical thickness Tox thereof (oxide film thickness). However, the approach to thin the gate oxide film reaches its limit at about 2 nm or less as described above. Therefore, aiming to increase the relative dielectric constant εr, the use of a high-k film as a gate insulating film has recently been discussed seriously. Typically, such a high-k film is formed by using a CVD method, including an atomic layer deposition (ALD) method, or a PVD method by sputtering or vapor deposition.
In the case of the first conventional example (see FIG. 4A to FIG. 4D), the HfSixOy layer 52, which is an interface reaction layer, grows when forming the HfO2 film 51, which is a high-k film. As a result, the equivalent oxide thickness (hereinafter referred to as “EOT”) of the gate insulating film as a whole increases. On the other hand, another method (hereinafter referred to as “second conventional example”) is proposed in the art, in which the entailing growth of the interface reaction layer is suppressed by vacuum reoxidation process, thereby sharpening the change of the composition distribution at the interface between the silicon substrate and the high-k film (Heiji Watanabe, Proc. of the 48th Meeting of the Japan Society of Applied Physics and Related Societies, 30p-YF-10, p. 859, 2001.3). Specifically, in the second conventional example, a chemical oxide having a thickness of 0.6 nm is formed on a silicon wafer, and then a thin zirconium (Zr) film is deposited thereon by electron beam evaporation, after which the silicon wafer is oxidized in an oxygen atmosphere that is depressurized to a ultra-high vacuum state (about 1.33×10−2 Pa), thereby producing a ZrO2/SiO2/Si layered structure.
With the first and second conventional examples, however, it is often the case that the device has a short lifetime, for which the device operates reliably, or poor insulation characteristics, as compared with a thermal oxide film of the same electrical thickness (i.e., a thermal oxide film with a smaller physical thickness but the same gate capacitance) and, needless to say, as compared with a gate oxide film (thermal oxide film) of the same physical thickness.
Moreover, in the first conventional example, it is known that the characteristics of the interface between a silicon substrate and a high-k film (hereinafter referred to as “Si/high-k interface”) are more likely to deteriorate than the interface between a silicon substrate and a thermal oxide film (hereinafter referred to as “Si/SiO2 interface”), and a large number of interface states occur at the Si/high-k interface. On the other hand, in the thermal oxide film, a strain occurs at the Si/SiO2 interface as its volume increases in the thermal oxidation process. This strain induces structural defects, thereby creating an interface state that functions as a carrier trap site, thus giving various adverse effects on the characteristics of the MOSFET, e.g., a dielectric breakdown of the gate oxide film or a decrease in the carrier mobility through the channel. However, since the degree of deterioration of transistor characteristics due to a gate oxide film is not so serious as compared with that due to a high-k gate insulating film, thermal oxide films have long been used as gate insulating films.
Furthermore, in the first conventional example, in addition to the presence of more interface states at an Si/high-k interface than at an Si/SiO2 interface, a high-k film has more fixed charge therein than a thermal oxide film, thereby resulting in increased scattering of carriers in the channel and thus deteriorating the mobility characteristics.
Thus, it is desirable to provide a gate insulating film that has Si/SiO2 interface characteristics and a small EOT. However, when a high-k film is deposited on an underlying oxide film (chemical oxide) on a silicon substrate, as in the second example, unexpected interface states occur at the Si/high-k interface, thereby leading to an increase in the leak current via the interface states.